Fermi level pinning in Si, Ge and GaAs systems - MIGS or defects?

Si, Ge and III-V based MOSFETs can be limited by Fermi level pinning (FLP) at their interfaces. Pinning can arise from either intrinsic (metal induced gap states, MIGs) or extrinsic (defects) mechanisms. Identifying the correct mechanism is not trivial, as both mechanisms follow similar chemical trends. However knowing the correct mechanism is important, as only extrinsic mechanisms can be corrected by varying processing conditions. Our purpose is to clarify Schottky barrier concepts and provide some atomic models of unpinned GaAs - oxide interfaces.