A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI

A CMOS 6-b, 200 MSample/s, (MS/s) flash A/D converter (ADC) with 3 V power supply has been developed for a mixed-signal partial-response maximum likelihood (PRML) read channel LSI. In a CMOS flash ADC with chopper comparators, all comparators are auto-zeroed prior to each conversion. As a result, half of the available comparison time is spent autozeroing. To improve conversion rate and performance when included in a mixed-signal LSI, the auto-zeroing rate was reduced using a newly developed "interleaved auto-zeroing" (IAZ) architecture. Less frequent auto-zeroing also reduces kickback noise to the analog input and reference resistor string and power supply noise. In addition, the comparator output-swing is limited to improve recovery from large overdrives by adding diode connected transistors. This "output-swing limiting comparator" (OLC) improved the response to high frequency analog inputs. A conversion rate of 200 MS/s was achieved in the PRML read channel LSI using the IAZ architecture and OLC. This ADC was fabricated with single poly-Si, double-Metal, 0.5-/spl mu/m CMOS technology.