A 10b 1MS/s 0.5mW SAR ADC with double sampling technique

This paper introduces the 10 b 1 MS/s 0.5 mW SAR ADC with double sampling technique. It utilizes the double sampling technique to reduce power. The SAR ADC is implemented in CMOS 1P8M 65 nm technology and occupies 0.111 um
²
. The maximum sampling rate is 1 MS/s. The simulated SNDR and SFDR are 55.6 dB and 62.7 dB, respectively at input frequency of 484 kHz. Power consumption of the data converter is total 507 uW with 1.2-V supply.