A high-speed differential receiver with low-power interleaved direct decision feedback equalizer

A high-speed differential receiver with low-power interleaved direct decision feedback equalizer (DFE) is proposed and designed with a 0.18 um CMOS process. To save the power consumption, the new feedback topology is introduced. This architecture feeds back the previous bit to the proposed latch block. As a result, the adder blocks can be removed obtaining the low-power interleaved direct DFE. The current mode logic (CML) latch with embedded adder is used to reduce power consumption.