A 11-mW quadrature frequency tripler with fundamental cancellation

A low-power quadrature frequency tripler is designed by using the sub-harmonic mixer configuration. The circuit is implemented in CMOS 0.180 um technology. The frequency tripler consumes 11.5 mW, while the output buffers consumes 43.1 mW, all with supply voltage of 1.8 V. The fundamental Harmonic Rejection Ratio (HRR
₁
) achieves more than 35 dB, and the conversion gain achieves -4.2 dB at output frequency of 4.5 GHz. The entire chip area occupied 1.4 × 1.1 mm
²
.