A VHDL based functional compiler for optimum architecture generation of FIR filters

This paper describes an integrated CAD methodology for rapid architecture generation of FIR filters in VHDL format for a wide range of filtering applications. The key element in the design methodology is the functional compiler which accepts functional parameters and generates technology independent (and retargetable) architecture in VHDL format. The filter compiler produces optimum architectures for general, linear-phase and decimation FIR filters. Optimum architecture derivation using dependence graph (DG) and signal flow graphs (SFGs) based technique is illustrated for decimation FIR filters. Using the compiler, a 2.4 mm/sup 2/ decimation FIR test chip has been implemented in 1.0 /spl mu/m CMOS and is expected to achieve a speed of 120 MHz while dissipating 0.24 W.