Assessing merged DRAM/logic technology

This paper describes the impact of the DRAM process on the logic circuit performance of Memory/Logic Merged Integrated Circuits and the alternative circuit design technology to offset the performance penalty. Three state-of-the-art logic processes (0.5 /spl mu/m, 0.6 /spl mu/m, and 0.8 /spl mu/m) and two state-of-the-art DRAM (64 Mb and 256 Mb) processes have been selected for the study. The simulation results show that the logic circuit performance is degraded by about 22% on the DRAM process including increased interconnect delay due to less interconnect layers available in the DRAM process. The silicon area increased up to 80% depending on the number of nets and components when implementing the logic circuit in the DRAM process.