Structure and process development of wafer level embedded SiP (System in Package) for mobile applications

Recently the requirement for portable products, such as mobile phones, digital cameras, PDAs and game consoles, has been increasing rapidly and consumers want to easy to carry them and have multi-functions as well as lower price. So it's necessary to develop the semiconductor packages with thin and small size, high performance and low cost. And various types of SiP (system in package) technologies have been developed to satisfy these requests. The embedded packages are one or more chips are embedded at the inside of the substrate and one of the technologies to realize the packages with thin and small size and high performance but there is much room for improvement, such as reliability issues, yields, etc. Therefore, wafer level embedded SiP (WL-ESiP) which daughter chip is embedded on mother chip by mold compound without substrate has been developed. In this study, to confirm our wafer level embedded SiP structure and processes, feasibility test has been performed by fabrication of molded dies with 2 stacked dies at wafer level and verified by reliability tests of MSL2a, PCT (121?C/100%RH/2 atm), HTS (150?C) and TC (-65/150?C) for molded dies. To realize this embedded SiP, redistribution, solder and Cu bumping, flip-chip bonding, molding, Si and mold thinning and ball mounting technologies have been developed and applied at the wafer level. After feasibility test, to confirm the effect of the package size and material for the WL-ESiP, the reliability tests of MSL2a, PCT (121?C /100%RH/2 atm), TC (-40/125?C) and HTS (150?C) have been performed for molded dies with die sizes of 4 mm ? 4 mm and 6 mm ? 6 mm, 3 types of dielectric materials and 3 types of mold materials and the test vehicle with MC3 mold, D2 dielectric and 4 mm ? 4 mm size passed MSL2a, 168 hrs of PCT, 2000 cycles of TC and 1000 hrs of HTS. Also, the stress simulation of mold dies has been performed and the location with maximum stress has been confirmed. As a result of reliability tests and stress simulation for the molded die, WL ESiP test vehicle with daisy chain has been designed and fabricated to evaluate the package level and board level reliabilities. The size of mother and daughter chips is 4 mm ? 4 mm and 2.95 mm ? 2.31 mm respectively and daughter chip has 70 um thickness. For the fabricated WL-ESiP, package level reliability tests of MSL2a, PCT (121?C /100%RH/2 atm), TC (-40/125?C) and HTS (150?C) has been performed. And TC (-40/125?C) and drop (1500 G/0.5 ms) tests will be also performed at board level.