Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions

This paper presents a pseudo-2-D surface potential model for the double-gate tunnel field-effect transistor (DG-TFET). Analytical expressions are derived for the 2-D potential, electric field, and generation rate, and used to numerically extract the tunneling current. The model predicts the device characteristics for a large range of parameters and allows gaining insight on the device physics. The depletion regions induced inside the source and drain are included in the solution, and we show that these regions become critical when scaling the device length. The fringing field effect from the gates on these regions is also included. The validity of the model is tested for devices scaled to 10-nm length with SiO
₂
and high-¿ dielectrics by comparison to 2-D finite-element simulations.