Design and implementation of high performance FPGA control for permanent magnet synchronous motor

The paper reports the design of an FPGA implementation of an high performance control for permanent-magnet synchronous motors (PMSM) with sinusoidal flux distribution. The objective of this work is to test a single chip FPGA solution in order to simplify the HW, to allow an easy reconfiguration of the control architecture, and mainly to make a step towards a System on Programmable Chip (SOPC) sensor-less PMSM drive exploiting the high computational throughput of the adopted device. The functional blocks are described in details and simulation results are reported for each of them. Experimental verification has been carried out, with an Altera Stratix II device, with a 5 kW brushless motor. The results show how the proposed platform allows for the sensorless and flux estimation algorithms implementation which will be further developed and tested.