Correlated power noise generator as a low cost DPA countermeasures to secure hardware AES cipher

To secure cryptography hardware implementation many works are focusing on side-channels attacks. For such attacks, several different countermeasures can be done at different levels abstraction. But all published countermeasures lead to a significant area and power consumption overhead. In this paper, we present a new countermeasure against DPA attack which also leads to very small implementation compared to existing countermeasures such as the most used: masking schemes. The proposed approach is to use a correlated power noise generator to removes the design power correlation with the secret key. Its efficiency is proved with a practical DPA attack realization on Actel Fusion FLASH FPGA and Xilinx Virtex 4 SRAM FPGA. With the proposed countermeasures, the full 128-bits AES implementation on Xilinx Virtex 4 has a smaller area overhead (12.78 times less) than masking scheme countermeasures.