FPGA implementation of polyphase decomposed FIR filters for interpolation used in Δ-Σ audio DAC

This paper describes a synthesis design from the MATLAB model into VHDL of a digital interpolation filter algorithm, used in a Δ-Σ Digital-to-Analog converter (DAC), intended for Professional digital audio system. The whole filter system simulation, VHDL implementation and Field Programmable Gate Array (FPGA) verification are processing. The Register Transfer Level (RTL) simulation result show an achieving a high resolution of a 22.5-bit at a switching rate of 8.192 MHz and a small area less than 50% of the total chip. Timing analysis indicates any violation of temporal constraints and the worst-case maximum clock speed of the design can attain a 500 MHz.