$(1/3) \times \hbox{VDD}$-to- $(3/2) \times \hbox{VDD}$ Wide-Range I/O Buffer Using 0.35- $\mu\hbox{m}$ 3.3-V CMOS Technology

A 0.9/1.2/1.8/2.5/3.3/5.0-V wide-range input/output buffer carried out using a typical complementary metal-oxide-semiconductor (MOS) 2P4M 0.35-μm process is proposed in this brief. An input buffer with a logic calibration circuit is used for receiving a low voltage signal. A novel floating n-well circuit is employed to remove the body effect at the output p-channel MOS (PMOS). Moreover, a dynamic driving detector is included to equalize the turn-on voltages for the output PMOS and n-channel MOS transistors. The worst-case duty cycle of the output signal can then be 54.2% in a low-voltage mode. The maximum output frequency of the proposed design is measured to be 17.9/27.9/35.3/70.1/79.2/60.0 MHz for VDDIO = 0.9/1.2/1.8/2.5/3.3/5.0 V, respectively. The power consumption is 553 nW at the worst simulation case of [SS, 100°C] and 330 nW by on-silicon measurement.