High level modelling and performance evaluation of address mapping in NAND flash memory

Flash memory has several particularities compared to other types of memory. First, a write operation should be preceded by an erase operation. Second, erase operations can only be performed in a unit much larger than the write unit. Finally, each erasable unit has a limit number of possible erase operations. To address these problems, an intermediate software layer called flash translation layer is used to perform address translation based on a mapping algorithm. The used mapping scheme is very important in deciding the performance and lifetime of flash memories. In this paper, we present a high level model for flash memory system allowing evaluating the impact of the address mapping algorithm on the performance of flash memory. We show the applicability of the performance estimation on one of the most popular and sophisticated address mapping scheme.