Design and implementation of FPGA based interface model for scale-free network using I2C bus protocol on Quartus II 6.0

To enable devices to communicate with each other over a serial data bus without data loss, as well as to enable faster devices to communicate with slower ones, the I
²
C(Inter IC) protocol was put forward by Philips Semiconductors in January 2000. Ever since, there has been families of I
²
C enabled microcontrollers like the PIC18F452 from Atmel and TMS470 from Texas Instruments. However, configuring these microcontrollers requires a lot of programming and knowledge of the register structures, and hence they are not portable. In this paper, a generic design on an FPGA platform is presented, which does away with the need of any further programming while setting up the network. Also, the proposed model can be used both as a master and as a slave. The entire design has been coded in VHDL and verified using Quartus II 6.0.