CMOS programmable divider for Zigbee frequency synthesizer

This paper presents a 4 bit integer N CMOS programmable frequency divider with high speed and low power consumption. It is based on a dual-modulus prescaler, and programmable asynchronous and synchronous dividers. It works up to 3.4 GHz frequency clock. It is tested in PLL for 2.4 GHz band Zigbee standard. All results are taken from simulating extracted layout. It is implemented using Silterra 0.18 CMOS process, voltage supply 1.8 V, and consumes 0.7 mW.