Lower power, lower delay design scheme for CMOS tapered buffers

This paper proposes lower power, lower delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipation. As compared to the constant threshold voltage design based on a cost function of PT
²
, the proposed scheme can lead to either a power dissipation reduction of about 70% while maintaining the same delay, or up to 30% in power dissipation with 10% propagation delay reduction, respectively, in 65 nm technology with V
_DD
= 1V, minimum size gate capacitance, C
_g
= 1.5 fF, and minimum size output capacitance, C
₀
= 1fF. Closed form expressions that give the optimum threshold voltage and number of stages are presented.