CAN bus analyzer and emulator

A need arises when using CAN buses to monitor the data on the bus as well as having the ability to inject further data onto it. This provides the ability to fully test a CAN network on both the frame level and the bit level. This paper introduces a new CAN bus analyzer and emulator. The proposed system on chip (SoC) is verified by simulation and implementation on FPGA board. Real time results show the efficiency of the SoC in bus analysis and CAN node emulation.