A robust and automated methodology for LVS quality assurance

In IC design flow, layout versus schematic (LVS) is a key step in layout verification phase, and writing the LVS rule file is considered a tough task that requires considering many details in order to give the verification tool the desired level of layout-understanding power. However, getting a hundred percent efficient rule file in the first shot is not likely to happen, therefore QA techniques on the LVS rule file are required to be developed in order to point out errors and limitations in it. The common and straightforward procedure for doing this is to run LVS using the rule file of concern on manually created layouts (Test Cases) of pre-known LVS results. Of course this procedure consumes time and effort comparable to that consumed in writing the rule file, especially in new technologies where the number of devices is noticeably higher. Another drawback of that common procedure is that when test cases are required to be fully connected (not just single devices), the whole process becomes design kit dependant; i.e. the design kit has to be ready in order to create the test structures. In this paper we introduce a methodology for automating the whole process of generating test patterns to be used in testing the LVS rule deck. Our work had not only dramatically reduced the time and effort required for the rule file QA process but also eliminated any possible human errors and allows for different checker options to be performed simultaneously or on separate runs. In this paper the limitations of the current flow is discussed in details and compared to the methodology proposed, and the paper is concluded with a brief description of the results obtained using the code developed and tested on a 90 nm technology PDK.