Formal verification of analog and mixed signal designs

System-on-chip (SoC) is becoming a core technology in a growing range of consumer and other electronic devices. Cornerstones of SoC designs are analog and mixed signal (AMS) designs, which are integrated circuits required at the interfaces with the real world environment. To respond to certain challenges and due to the limitations of simulation techniques (long simulation runs, inaccurate results, etc.), formal verification of AMS designs emerged as a new area of research. It is a technology based on using computerized algorithms to the mathematical reasoning about the correctness of designs and has been used in the past two decades exclusively for digital design and software verification. This paper provides a review of the state-ofthe-art in AMS formal verification and present advanced approaches that handle continuous as well as discrete-time designs with both linear and non-linear behaviors.