Subthreshold minority-3 gates and inverters used for 32-bit serial and parallel adders implemented in 90 nm CMOS

32-bit serial and parallel adders exploiting minority-3 elements and inverters only, are presented, including chip measurements. The implementation is done in a standard triple-well 90 nm CMOS process. Measurements also demonstrate that the digital abstraction may be maintained for basic building blocks under the presence of stuck-open faults and defect transistors, for a redundancy factor, R, of only 2. R = 2 combined with shorted driven nodes is lower than the traditional R=3 in combination with majority voting. For the serial adder the MSB as a result of toggling LSB in one of the 32-bit input words was adequately produced for 9 out of 10 prototype chips for a V
_dd
of 250 mV, and for 5 prototypes when reduced to 200 mV. For the 32-bit parallel adder these numbers were 10 out of 10, and 4 out of 9 respectively. A new minority-3 gate is proposed, having a very regular layout, that could make it a suitable candidate for certain future nanocmos circuits. The energy effeciency for serial versus parallel adders, combined with the shape of their layout, may make them good candidates to be combinated with redundancy for ultra low power, subthreshold, defect-tolerant arithmetic circuits.