Implementation of a hardware functional verification system using SystemC infrastructure

The implementation of a verification environment to check the behavior of a device-under-test using SystemC infrastructure is presented in this paper. SystemC is generally adopted in a system-level design methodology because of the capability of architectural model description and hardware/software co-design. The verification system implemented in this paper can explore design space using SystemC with a minor adaptation, and verify functional correctness of the progressively refined modules to RTL HDL. The infrastructure of the verification system uses intermediate user-defined channels as communication interface between variables of SystemC module and registers of Verilog module. SystemC modules of the verification system can be reused for other hardware component verification because of the object-oriented feature of SystemC. The functional verification of an UART is performed on the proposed verification system.