Design FPGA Based Implementation of MIMO Decoding in a 3G / 4G Wireless Receiver

In this paper, we address the implementation of FPGAs of Multi-Input-Multi-Output (MIMO) Decoder embedded in a prototype of 3G / 4G Mobile receiver This MIMO decoder is part of a multi-carrier code division multiple-access (MC-CDMA) radio system, equipped with multiple antennas at both ends of the link that is able to handle up to 32 users and provides raw transmission bit-rates up to 125 Mbps. The task of the MIMO decoder is to appropriately combine the signals simultaneously received on all antennas to construct an improved signal, free from interference, from which to estimate the transmitted symbols. The main motto of this is to design the FPGA based MIMO Decoder. To demonstrate this, MIMO Encoder is also included in this project. The Data links for Two symbol period were established and found that the MIMO decoder outputs follows the MIMO Encoder input. We report results using FPGA devices of the Xilinx family.