On the design of low phase-noise CMOS LC-tank oscillators

This paper describes theoretical as well as practical aspects in designing low phase noise LC CMOS oscillators. It starts with an overview of the different oscillator performance parameters found in a typical oscillator specification sheet. It also describes the LC-tank oscillation phenomena by analyzing a simplified LC oscillator circuit. Oscillator phase noise analysis is then introduced as a logical extension to the simplified LC oscillator model with noise perturbations included. The three most-common LC oscillator topologies, namely the Colpitts, cross-coupled NMOS, and NMOS-PMOS topologies are outlined and their trade-offs are explored. Passive device selection and modeling are another essential component in oscillator design. An overview of their different design and modeling techniques is introduced. Further, process characteristics have a big impact on device performance and hence on the overall oscillator performance which simulations can not accurately predict. The paper concludes by describing how on-wafer device characterization schemes through test chips can help improve device modeling and potentially identify any oscillator design weaknesses.