On the energy efficiency of analog circuits in nanoscale CMOS technologies

Energy efficiency plays an important role in the design of high performance analog integrated circuits. With the introduction of nanoscale (sub-100 nm) CMOS technologies, it is becoming increasingly difficult to maintain the energy efficiency for high accuracy analog circuits. This paper derives figure-of-merit (FOM) limits for general analog circuits and discusses some design criteria that can be utilized to mitigate the impact of scaling on energy efficiency.