Analog implementation of the FDTS/DF detection algorithm for magnetic recording

An analog implementation of the fixed delay tree search algorithm for magnetic recording detection is presented. The circuit is designed using a 1.2 /spl mu/m BICMOS process with NPN devices with an f/sub t/ of 12 GHz, and provides a reference for the feasibility of an analog implementation. Composite simulation results of all the system blocks suggest operating speeds in excess of 100 MSamples/s with a total power consumption of less than 1 W.