Ge Epitaxial Refill Deposition Techniques for Fabricating Pedestal Transistor Structures

An etch-epitaxial refill technique is described for the fabrication of integrated high-speed Ge transistor structures having a pedestal configuration. The device areas surrounding 0.1 ohm-cm mesa structures were refilled with Ge having a resistivity range of 1 to 10 ohm-cm, providing low parasitic capacitance in the passive area of the base-collector junction. Processes and techniques were developed for minimizing the ridge that tends to form at the edge of the deposited SiO
2
mask. Electrical properties and junction characteristics of the epitaxial regions are discussed and some device results presented.