A 64K FET Dynamic Random Access Memory: Design Considerations and Description

The major design considerations and design features of an experimental 64K-bit random access memory (RAM), implemented in a double polysilicon gate technology, are described in this paper. Design tradeoffs addressing power supply selection and chip configuration alternatives are presented. This is followed by a description of the 8K-word by 8-bit FET dynamic RAM which uses single-transistor cells with first-level-metal bit lines and second-level-metal stitched polysilicon word lines. Test results obtained on early engineering hardware chips fabricated with linear dimensions 1.2 times those of the base design are also presented.