Bipolar Circuit Design for a 5000-Circuit VLSI Gate Array

Ever-increasing gate-array chip circuit count and size pose challenges to the circuit designer, who must optimize the cell layout and power dissipation of logic circuits. This paper describes the design of a bipolar gate array for a 5000-circuit microprocessor. The physical design data obtained after completion of automatic placement and wiring are presented. The distribution of projected circuit delay for the 4437 nets is then calculated and this information is used to determine the selective increase in circuit power to reduce wide spreads in turn-off and turn-on delays. It is shown that this technique improves power/performance and has implications for future VLSI designs. It was also found that voltage drop violations were manageable even with the long net lengths occurring in this large VLSI gate array. Several commonly used bipolar circuit types are compared on the basis of capacitance drive capability at low power.