Exploiting instruction level parallelism with the DS architecture

A new architecture, DS, for exploiting instruction level parallelism is proposed in this paper. DS splits the program into two instruction substreams with the dominant one navigating the control flow and the subsidiary one carrying out the rest of the computational task. Compiler techniques associated with the DS architecture are discussed, with the goal of minimizing communication and balancing computation. Performance is compared with an aggressive 8-way superscalar processor. In general, DS can deliver the same IPC as the superscalar. This is achieved with less complex hardware and better potential for fast clock rates.