LAN interface chip and mixed-signal testing developments

This paper describes the local area network (LAN) semiconductor chip, from early development through volume manufacturing production, highlighting the testing achievements associated with its qualification and release to production. The paper is divided into two sections dealing with laboratory development and production in manufacturing. The development section describes the importance of partitioning via latch-based boundaries, and how it reduced development cycle time by allowing independent debug and diagnostic tests. The development of tests to characterize the phase-lock loop (PLL) at application conditions and the evolution of these tests into efficient production test vehicles are discussed. Techniques are described that provide new approaches to analog testing, focusing on adapting a production digital tester to meet the characterization and production requirements of a very sensitive PLL/receiver/transmitter analog design. The manufacturing discussion is centered around three areas, wafer testing, yield learning, and reliability. Unique concepts in each area are presented, along with detailed descriptions of specific applications.