Design for testability and diagnosis in a VLSI CMOS System/370 processor

This paper describes the design for testability and diagnosis in an IBM System/370 processor based on VLSI CMOS technology. The design incorporates built-in pseudorandom-pattern self-test and the boundary-scan technique. This technique permits the migration of tests generated for component-level to higher-level packages such as printed circuit boards and the system. Consequently, the expense for testing of higher-level packages can be reduced, and the test equipment for the processor can be simplified. The design also offers economical diagnostic capability.