Memory reduction for HDTV decoders

In this paper, we propose a low-cost memory reduction scheme which can reduce the memory requirement for full HDTV decoding from 12 MB to 4 MB. This scheme uses a switchable architecture that allows HDTV decoding with scalable memory reduction ratios. Depending on the input format and the amount of available memory, the scheme performs 1/4 or 1/2 memory reduction or no memory reduction. The 1/2 memory reduction is achieved by performing a block-based Hadamard transform followed by appropriate scalar quantization. The Hadamard transform has good signal energy compaction and a low computational cost. Appropriately designed nonuniform scalar quantizers take advantage of the statistics of the Hadamard transform coefficients and compress the data to match the 1/2 memory reduction target. The 1/4 memory reduction is achieved by 1/2 horizontal decimation followed by the 1/2 memory reduction scheme. Experimental results show that the proposed memory reduction schemes achieve good performance at very low computat ional cost, which makes them very attractive for digital TV applications.