An Overview of Data Bandwidth Hierarchy for an Embedded Stream Processor

The overall speed of computation is determined not just by the speed of the processor, but also by the ability of the memory system to feed data to it. Imagine is a novel image processor which is constructed by a research group of Stanford University. A brand new data bandwidth hierarchy of this processor is introduced in this article. This new data bandwidth hierarchy is constructed by local register file(LRF), stream register file(SRF) and main memory. LRF is used by the ALU clusters. SRF looks like cache in traditional processor. But SRF is a specific unit in stream processor. SRF is used as a stream load/store unit in stream processor. Using this kind of data bandwidth hierarchy the image processing speed is improved greatly.