Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Recently, minimizing the standby power is considered as a critical issue in high-density, mobile CMOS technology. One of the major sources of the leakage current in off-state of ultra-small MOSFET is gate-induced drain leakage (GIDL) which is mainly composed of inter-band and trap-assisted tunneling. By virtues of reduced intra-junction and punch-through leakage currents, threshold voltage controllability, and higher current drivability [1], SOI FinFETs are utilized in most recent CMOS circuits [2]. In this work, half-pitch (HP) 32 nm SOI FinFETs are designed for LSTP considering GIDL by device simulation [3] with regard to junction doping profile. For more accurate results, various models for carrier mobility, gate current, recombination, band-to-band and trap-assisted tunneling, and quantum effects have been activated. Fig. 1 and 2 show the schematic view of the device with its circuit symbol [4] and control variables, distance and gradient near a junction, respectively. Although a FinFET can be used as either 3-terminal (3-T) or 4-T device by separating processes, only the 3-T device has been characterized for a reference. Peak-to-gate distance can be obtained by relation of (underlap length)=(distance)-(gradient). Meeting the requirements for HP 32 nm LSTP device suggested by a technology roadmap (ITRS) [5], physical channel length, thickness, and gate oxide thickness are 20 nm, 8 nm and 1.4 nm, respectively. n
⁺
peak doping concentration is As 1×10
²¹
/cm
³
(Gaussian distribution) and the Si channel is lightly doped with 1×10
¹⁶
/cm
³
B to avoid dopant fluctuation. Fig. 3 shows the threshold voltages by constant current method at I
D
=0.1 μA as a function of gradient. Fig. 4 demonstrates off-state currents (I
D
@(V
G
, V
D
)=(0V,0.9V)) under different gradient conditions. The dotted line indicates a reference current, 24.4 pA/μm, suggested be ITRS. All the currents have been normalized by unit width as well as factor 2 (double channels). Fig. 5 depicts on-state current (I
D
@(V
G
=V
D
=0.9V)) as a function of gradient. Fig. 6 shows the current ratio (I
off
/I
on
) varying with peak-to-junction gradient. At a very small gradient, the ratios are distinctively different and become larger as the underlap increases while it saturates in the large gradient region, as shown in Fig. 6(a). On the other hand, investigating it in a linear scale, the tendency is reversed: the current ratio is degraded as the underlap length gets longer due to increased series resistance by elongated doping gradation [6]. Fig. 7 demonstrates quantitatively extracted drain leakage currents (GIDL) at different gradient conditions. Fig. 8(a) and (b) explain the method of GIDL extraction: GIDL current is formulated as the integration of band-to-band and trap-assisted tunneling [7]. Thus, the models governing GIDL current, srh (Shockley-Read-Hall recombination), bbt.std (band-to-band tunneling), and trap.tunnel (trap-assisted tunneling), can be switched on/off to identify the difference in current as shown in Fig. 8(a). This is performed at the gate voltage where the second derivative of I
D
-V
G
curve is maximized, which is physically more accurate and reasonable than the existing method [8] in the sense that it can exactly locate the beginning point where the curvature is most rapidly changed by drastic GIDL enhancement. The point has been obtained as the gate voltage where the second derivative of the I
D
-V
G
curve smoothed by filtering the noisy currents has a local maximum as demonstrated in Fig. 8(b). In Fig. 9(a) and (b), GIDL currents are visualized graphically in a 3-D space of distance, gradient, and GIDL coordinates and a 2-D map with interpolated colors, respectively, for easier understanding of the combinational effects of distance and gradient on GIDL. The map implies that the underlap is essential and more graded junction is desirable for minimizing GIDL at a given underlap length. Although there can be a number of feasible dots on the map, the current ratio should be considered simultaneously for more rigorous design.