The effect of die-level stress variations on device performance

The performance improvement associated with the intentional manipulation of stresses on the transistor scale is an integral part of device fabrication at advanced technology nodes. However, comparatively little attention is given to stress management at within-die and within-wafer length scales. This paper describes the use of a stress measurement technology, the Coherent Gradient Sensing (CGS) interferometer, to characterize the evolution of stresses up through source/drain anneal in a process flow. The CGS technique facilitates the generation of high-density stress maps (>700,000 points on a 300 mm wafer) such that the stresses induced die-by-die and process-by-process can be tracked in detail. Results are presented showing the relationship between die-level stresses and device performance. The correlation between die-level stresses and device performance indicates that stress variations account for ~35 to 50% of the performance variation observed. The use of these correlations to identify critical process steps is discussed, with particular attention given to the role of different thermal processes.