TopGen: A new algorithm for automatic topology generation for Network on Chip architectures to reduce power consumption

The number of processors and storage elements on a single chip increased significantly as a result of shrinking technology sizes. However, this rapid component increase on systems made the traditional bus-based communication structures problematic since the components needed long interconnection lines. The distribution of the clock over the entire chip became almost impossible on huge systems because of the clock propagation and synchronization. Additionally, the power consumption on the interconnection lines became more critical than the computational blocks. Network-on-chip (NoC) has been introduced in the beginning of this millennium as an alternative to bus-based and point-to-point communication structures. NoC architectures made it possible to limit the length of interconnections by dividing them among routers and the components are connected the routers allowing sending data any time without synchronization problems. However, these additional components also brought extra power consumption on the system. To minimize this power consumption, the given application should be mapped on the optimized topology, which can be either a regular topology or irregular topology. Irregular topologies are a good candidate for optimization; however, there is still need for algorithms for topology generation. In this paper, we present an irregular application specific topology generation algorithm (TopGen) for Network-on-Chip architectures. We applied TopGen on some real multimedia benchmarks and compared with existing algorithms. We achieved up to 22% power savings.