The Implementation and Evaluation of Hardware/Software Co-Design Method for Fast Image Processing via FPGA

The Hardware/Software co-design method for fast image processing tasks is presented in this paper. The platform is a FPGA board, which is embedded with a soft processor as the main processor in the system, and a co-processor is designed using FSL (Fast Simple Link) to connect the main processor. The software application on the main processor can deal with general function, but can not afford the time-critical arithmetic because its main frequency is limited. According to the architecture and characteristics of arithmetic, to design a co-processor can result in dramatic acceleration. By using the co-processor, the result and resource occupied are given, which indicate that this method has the characteristic of high speed and steady performance.