Distributed Shared Memory Architecture for NoC-Based Multi-Processor

Network on chip (NoC) implements routers and links onto a single chip. NoC is scalable compared to bus for many-core system. When communication moves from bus to NoC, the single centric memory becomes congested node of network and bottleneck of performance. In this paper, we apply distributed shared memory architecture to a NoC-based multi-processor system. On this hardware platform, we ran a multi-thread application, and observed the improvement of network throughput and overall performance.