A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS

A 9 b 100 MS/s successive approximation register (SAR) ADC has been implemented in 65 nm CMOS, with an active area of 0.012 mm
²
. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1 dB (8.53 ENOB) and consumes 1.46 mW from a 1.2 V supply, resulting in an FOM of 39 fJ/conversion-step.