An interpolating clock synthesizer

A digital alternative to analog phase-locked loop (PLL)-based clock generators for microprocessors, denoted an interpolating clock synthesizer (ICS), is described. Using ROM-based digital waveform synthesis, the ICS implements a wide range of frequency multiples having the form P/Q, where P and Q are integers. The ICS outputs two synthesized clocks, one for the I/O interface having a 1/1 frequency multiple and one for the core having one of eight dynamically-selectable frequency multiples (1/1, 3/2, 5/3, 2/1, 5/2, 3/1, 15/4, and 5/1). The ICS uses a synchronous delay line as a coarse (T/sub p//30) timing reference, while through digital delay interpolation it achieves a fine delay resolution of 0.04 ns. Using a completely digital precision phase detector, the ICS achieves a DC skew of /spl plusmn/0.05 ns.