In-circuit hot-carrier model and its application to inverter chain optimization

An analytical in-circuit device lifetime model and design methodology for minimizing hot-carrier effects in an inverter chain are presented. Based on the model, in-circuit device lifetime, /spl tau//sub AC/, for hot-carrier induced degradation is given by /spl tau//sub AC/=/spl tau//sub DC//R, R/spl equiv//spl radic//spl pi//2/spl radic/Vcc/b/spl radic/(T/sub rise/.T/sub fall/)/T/sub c/ where /spl tau//sub DC/ is the device lifetime under a DC test, T/sub rise/ and T/sub fall/ are the rise time for input and fall time for output, T/sub C/ is cycle time and b is a constant. The model also shows that minimizing circuit delay in the inverter chain maximizes hot-carrier reliability.