A 210 Mb/s radix-4 bit-level pipelined Viterbi decoder

The design of a high-speed and compact parallel add-compare-select unit using a combination of algorithmic, logic and circuit techniques is described. The results are demonstrated by a 16-state, R=1/2, 210Mb/s Viterbi decoder, that out-performs the fastest single-chip implementation previously reported by a factor of 1.8 in terms of the throughput/area metric using the same process technology.