A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuits

This channel-less CMOS gate array family with 600 Mb/s simultaneous bidirectional I/O circuits use 0.5 /spl mu/m CMOS four-metal-layer-process technology. 610kG raw gates and 608 I/O circuits are integrated in a 15.7/spl times/15.7 mm/sup 2/ chip, housed in a 1000-pin-class package to obtain wide data bandwidth. Various SRAMs and ALUs can be embedded for speed and density. Register files made on gate-array-basic cells are also available. An on-chip PLL macro cell is necessary to reduce clock skew between LSI chips used in systems that operate at frequencies of more than 100 MHz. The PLL generates internal clock frequencies of 100 MHz to 400 MHz with 200 ps of peak to peak jitter.