SystemVerilog-based verification environment using SystemC custom hierarchical channel

A verification environment which is based on a constrained random layered test bench using SystemVerilog OOP is implemented in this paper to verify the functionality of DUT designed with synthesizable constructors of SystemVerilog. Although the uses of multiple inheritance in OOP appear to be less common than those of single inheritance, multiple inheritance is useful for creating class types that combine the properties of two or more class types. Because SystemVerilog OOP technique does not allow multiple inheritance, we adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog-based layered testbench using SystemVerilog DPI and ModelSim macro. SystemVerilog DPI provides a way to interface with any other foreign language. Functions and tasks registered to shared library using DPI can be called out like native ones. ModelSim recently supports SystemC simulation with built-in compiler for SystemC design unit. In order to simulate SystemC design unit with ModelSim, the SystemC design unit should be modified using some macros provided by ModelSim. In this paper, FIFO channel frequently used in high-level communication is designed as a custom hierarchical channel which has three base classes; sc_channel, channel interface, and data payload interface. The low-layer components of the SystemVerilog-based layered testbench communicate with DUT using virtual interface, and other components can communicate with each other using FIFO channel. DUT in this paper includes BFM because most IPs designed for SoC are connected to a bus and controlled through the bus.