A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications

In this brief, we propose a lower error and ROM-free logarithmic converter. The proposed converter can lead to area-efficient hardware implementation as it avoids the need for a ROM by employing simple computation units for logarithmic approximation. Our proposed logarithmic conversion algorithm partitions the exact logarithmic curve into two symmetric regions such that the slopes in the two regions that are used for logarithmic approximation are inversed. Simulation results show that the proposed algorithm achieves an error range and percentage error range of only 0.045 and 3.339%, respectively, which outperforms previously proposed one-region and two-region conversion methods. We have implemented the proposed logarithmic converter using 0.13-¿m CMOS technology, and the latency is 2.8 ns. The proposed converter can be used to reduce the overhead of computation-intensive operations for real-time digital-signal-processing applications.