A ultra fast Euclidean division algorithm for prime memory systems

A fast way of computing quotients and remainders by numbers belonging to the class 2
ⁿ
± 1 has been presented, and the related hardware implementations described. The main interest of this technique lies in its applications to address skewing and address mapping in parallel memory systems. Although the proposed implementations are based on two input adders, the basic principles can be extended in a straigthforward manner to three input adders, allowing even faster modular reduction / division circuits to be assembled.