A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order $\Delta\Sigma$ Modulator in 90-nm CMOS

A 10 Gb/s receiver with a digital CDR uses a track-and-hold-type linear phase detector (LPD) and charge-redistribution first-order ΔΣ modulator. It has low quantization error and high loop bandwidth due to the use of the LPD and maintains the advantages of a digital CDR such as low power consumption, small area, fast locking time, and low-jitter recovery clock because no internal VCO is needed. The CDR tracking bandwidth is 20 MHz and high-frequency jitter tolerance is 0.42 UIpp at 10
^-12
BER. Power consumption of LPD is 2.6 mW while the entire receiver consumes 65 mW.