Generalized Pipelined Tomlinson–Harashima Precoder Design Methodology With Build-In Arbitrary Speed-Up Factors

In Tomlinson–Harashima (TH) precoding, the feedback filter (FBF) of a decision feedback equalizer (DFE) and the modulo devices are implemented at the transmitter. Because the TH precoders contain nonlinear feedback loops, it restricts their development for high-speed applications. With very large output levels of the modulo devices in the TH precoders, it is difficult to apply look-ahead and precomputation techniques to pipeline the TH precoders which are usually useful to pipeline IIR filters and DFEs. Among existing works of high-speed TH precoder designs, Gu and Parhi derived two pipelined TH precoder designs (PIPTHP1, 2). The architectures of these two designs seem to be very different and have their-own pros and cons. In this paper, we propose a two-time pipelining scheme to pipeline the TH precoders, which enables us to develop a generalized TH precoder architecture. PIPTHP1 and PIPTHP2 are derived by only applying the first-time and second-time pipelining schemes, respectively. Hence, both the designs can be considered as two extreme cases of the proposed designs. In conclusion, for a given design specification, the proposed scheme can provide tradeoffs between hardware complexity and output dynamic range, which leads to a near-optimal solution based on these design criteria. Therefore, the proposed scheme provides more degrees of freedom for the design trade-offs of high-speed pipelining TH precoders with build-in arbitrary speedup factors.