Whole-chip ESD protection design verification by CAD

CAD is essential to simulation, design and synthesis of on-chip ESD protection circuitry to ensure design prediction and verification at whole-chip level. This paper reviews a new function-based ESD CAD platform and design methodology, including arbitrary ESD protection device extraction algorithm, smart parametric ESD checking mechanism, smart ESD zapping simulation flow and new CAD tools enabling whole-chip ESD protection design verification. Practical design examples are presented.